The present invention relates to an internal address determining device for a semiconductor memory device, which internal address determining device can reduce the time required for determining the internal address.
In general semiconductor memory devices, internal addresses for memory access are determined based on externally provided address signals or address signals preliminarily stored in an address counter. In FIGS. 4 and 5 are shown a circuit diagram and timing chart for an internal address determining device in a conventional semiconductor memory device. The internal address determining device shown in FIG. 4 enables operations called CAS BEFORE RAS REFRESH mode and EXPANDED NIBBLE mode operations, for example, except for a normal mode operation.
The CAS BEFORE RAS REFRESH mode is a refresh mode in which a column address strobe (CAS) signal falls down before a row address strobe (RAS) signal does and when the row address strobe signal falls down, a refresh operation starts. Generally in a refresh mode, only row addresses are required to be provided. In the CAS BEFORE RAS REFRESH mode, the row addresses are automatically or internally provided from an internal counter. The internal counter is incremented by one each time a refresh row address is read therefrom, and therefore there is no need to provide refresh row addresses from the outside.
The EXPANDED NIBBLE mode is a mode for enabling a high speed access by inputting column address strobe signal as a clock pulse while keeping a row address strobe signal active. In this mode, a certain external column address following a certain external row address is initially input in response to a first clock pulse of the column address strobe signal. However, column addresses subsequent to the certain column address are read from an internal counter sequentially in response to subsequent clock pulses while the row address strobe signal is active. Therefore, once a first address is determined, there is no need to input column addresses from the outside from the second clock pulse of the column address strobe signal on.
In the conventional internal address determining device, an input section 101 has an inverter 108 and a NAND gate 107. To the NAND gate 107 are input a row address strobe signal RAS and an external address signal .phi.106 which consists of an external row address and an external column address. The external address signal .phi.106 in the input section 101 is passed by a transfer gate 106 when the transfer gate 106 receives a control signal .phi.101 generated by a timing circuit 104 for controlling the external address signal input timing. The external address signal .phi.106 having passed the transfer gate 106 is transferred to a multiplexer 103 after once latched by a first latch circuit 102. In response to an address select signal (described later) corresponding to a selected operation mode, the multiplexer 103 selects the external address signal .phi.106 or a refresh address signal .phi.107 stored in a refresh counter (not shown) or an expanded nibble address signal .phi.108 stored in an expanded nibble counter (not shown). Specifically, if the normal mode operation is selected, the multiplexer 103 selects and outputs the external address signal .phi.106 once latched by the first latch circuit 102, if the CAS BEFORE RAS REFRESH mode operation is selected, the multiplexer 103 selects and outputs the refresh address signal .phi.107 generated from the refresh counter (not shown), and if the EXPANDED NIBBLE mode operation is selected, the multiplexer 103 selects and outputs the nibble address signal .phi.108 generated from the nibble counter (not shown) although the first address is determined based on an external address. Output from the multiplexer 103 is latched and output as an internal address by a second latch circuit 105.
FIG. 5 shows the timing at which the above internal address determining device for a semiconductor memory device operates. Note that in FIG. 5 the solid line indicates operation timing during the normal mode operation, the dotted line indicates operation timing during CAS BEFORE RAS REFRESH mode and the dot-dash line indicates operation timing during the EXPANDED NIBBLE mode.
The control signal .phi.101 generated by the timing circuit 104 is applied to the transfer gate 106, which then transfers the external address signal .phi.106 from the input section 101 to the first latch circuit 102, as described above.
The multiplexer 103 is provided with an external address select signal .phi.102 of a high level during the normal mode operation, a refresh address select signal .phi.103 of a high level during the CAS BEFORE RAS REFRESH mode operation, and an expanded nibble address select signal .phi.104 of a high level during the EXPANDED NIBBLE MODE. The multiplexer 103 then selects and outputs the external row and column address signals .phi.106 transferred from the first latch circuit 102, or refresh address signal .phi.107 read from the refresh counter, or expanded nibble signal .phi.108 read from the expanded nibble counter, in accordance with a selected operation mode or address select signal of high level.
The second latch circuit 105 then latches the multiplexed address signal output from the multiplexer 103.
As described above, in the conventional internal address determining device, the external address signal .phi.106 is latched by the first latch circuit 102 after the external address signal .phi.106 is input into the input section 101, then the latched external address signal .phi.106, refresh address signal .phi.107, or expanded nibble address signal .phi.108 is selected by the multiplexer 103, and the selected address signal is again latched by the second latch circuit 105. Therefore, much time is required for an internal address to be finally determined.